1. Field of the Invention
The present invention relates to a pixel circuit, a solid-state image sensing device, and a camera system represented by a CMOS image sensor.
2. Description of the Related Art
Recently, CMOS imagers have widely been used for application of digital still cameras, camcorders, surveillance cameras, etc., and the market has been growing.
The CMOS imager converts light entering each pixel into electrons using a photodiode as a photoelectric conversion device and accumulates them in a fixed period, and then, digitizes and outputs a signal reflecting the amount of accumulated charge to the outside.
FIG. 1 shows an example of a pixel circuit containing four transistors per unit pixel.
A unit pixel circuit PX1 has a photodiode 1, a transfer transistor 2, a reset transistor 3, an amp transistor 4, a selection transistor 5, an accumulation node 6, and a floating diffusion (FD) node 7.
The gate electrode of the transfer transistor 2 is connected to a transfer line 8, and the gate electrode of the reset transistor 3 is connected to a reset line 9. The gate electrode of the amp transistor 4 is connected to the FD node 7, and the gate electrode of the selection transistor 5 is connected to a row selection line 10. Further, the source of the selection transistor 5 is connected to a vertical signal line 11.
A constant-current circuit 12 and a sensory circuit 13 are connected to the vertical signal line 11.
In the pixel circuit PX, light entering a silicon substrate of the pixel generates a pair of an electron and a hole and the electron of them is collected and accumulated in the node 6 by the photodiode 1. The electron is finally read out as a signal to the vertical signal line 11.
Typically, such pixels are arranged in a matrix in the CMOS imager, and the vertical signal line 11 is shared among plural pixels in the column direction and the transfer line 8, the reset line 9, and the row selection line 10 as gate control lines for turning on/off of the respective transistors are shared among plural pixels in the row direction.
The pixel access is provided collectively in units of rows by driving of the transfer line 8, the reset line 9, and the row selection line 10 as the gate control lines.
The analog signal readout into each vertical signal line 11 is sensed by the sensory circuit 13, AD-converted, and output.
As below, a specific operation of charge accumulation and readout will be explained with reference to FIGS. 2A to 2E.
FIGS. 2A to 2E show a timing chart of the pixel circuit in FIG. 1.
Prior to charge accumulation, resetting is first performed. This turns the reset line 9 and the transfer line 8 into the high level and turns on the reset transistor 3 and the transfer transistor 2. This is an operation of transmitting the power supply voltage of 3 V, for example, to the accumulation node 6 of the photodiode 1.
Thereby, the potential of the accumulation node 6 rises and the electrons accumulated therein are withdrawn.
In a currently predominant HAD (Hole-Accumulation Diode) structure, the accumulation node 6 is formed by an n-type embedded diffusion layer sandwiched between p-type layers, and completely depleted with all of its electrons ejected.
Then, the transfer line 8 is turned into the low level and the transfer transistor 2 is turned off, and thereby, the accumulation node 6 is floated and new charge accumulation is started. During charge accumulation, typically, the reset transistor 3 is also turned off, however, it may be kept on.
Generally, the reset operation of the pixel is used as an electronic shutter operation of the CMOS image sensor.
Next, the readout operation of the accumulated charge will be explained.
First, the row selection line 10 is turned into the high level and the selection transistor 5 is turned on, and the amp transistor 4 of the pixel is connected to the vertical signal line 11.
Here, the vertical signal line 11 and the constant-current circuit 12 connected to the amp transistor 4 form a source-follower circuit, and the potential Vf of the FD node 7 as its input and the potential Vsl of the vertical signal line 11 as its output have a linear relationship with a variation ratio nearly one.
That is, given that the current value of the constant-current circuit 12 is i, the following equation ideally holds.i=(½)×β×(Vf−Vth−Vsl)2//β is constant
Here, (Vf−Vth−Vsl) is constant and the variation of Vf is linearly reflected on Vsl.
That is, the source-follower circuit operates as an amp circuit with gain of nearly one, and the potential Vsl of the vertical signal line 11 is modulated to follow the change of the potential Vf of the FD node 7 as the input node.
Here, the reset line 9 is turned into the high level and the reset transistor 3 is turned on, and thereby, the power supply voltage of 3 V is transmitted to the FD node 7.
Further, the reset line 9 is turned into the low level and the reset transistor 3 is turned off, and thereby, the FD node 7 is floated.
Under the condition, the first sensing of the potential Vsl of the vertical signal line 11 is performed using the sensory circuit 13. This is readout of the reset signal.
Then, the transfer line 8 is turned into the high level and the transfer transistor 2 is turned on, and thereby, the electrons accumulated in the accumulation node 6 flow into the FD node 7 as the input node of the source-follower.
In this regard, when the potential of the FD node 7 is sufficiently deep, i.e., a high potential, all of the electrons accumulated in the accumulation node 6 flow into the FD node 7 and the accumulation node 6 is completely depleted.
Here, the transfer line 8 is turned into the low level and the transfer transistor 2 is turned off, and the second sensing of the potential of the vertical signal line 11 is performed using the sensory circuit 13. This is readout of the accumulated signal.
The difference between the first sensing and the second sensing of the Vsl accurately reflects the amount of charge accumulated in the accumulation node 6 through the exposure of the photodiode 1.
The CMOS imager digitizes the difference and outputs it to the outside as a signal value of the pixel. The electron accumulation time of each pixel is a period between the reset operation and the readout operation, and exactly, a period T1 from turning off of the transfer transistor 2 after resetting to turning off for readout.
The more detailed explanation of the behavior of the signal lines is that the potential of the FD node 7 slightly varies due to the influence of coupling when the reset line 9 drops to the low level and the level of the transfer line 8 is raised and lowered. Further, the vertical signal line 11 following that is affected in the same way.
The influence of the coupling from the transfer line 8 is cancelled out between rising and falling, and the influence of the coupling from the reset line 9 is cancelled out by the difference between the first sensing and the second sensing.
In this manner, generally, in the CMOS-type imager, the accumulated electron generated by the photoelectric conversion device is converted into an analog signal of the vertical signal line 11 via the amp circuit with respect to each pixel and transmitted to the sensory circuit 13.
Further, the analog signal is converted into a digital signal by an AD converter and output to the outside of the chip.
This contrasts sharply with a CCD-type imager in which the accumulated electrons themselves are vertically and horizontally transferred by CCD transfer immediately before the amp circuit for chip output.
FIG. 3 shows a circuit configuration of charge transfer from the photodiode 1 to the FD node 7 as the source-follower input node in FIG. 1 by extraction.
At charge accumulation, electrons generated by photoelectric conversion in the photodiode 1 are accumulated in the accumulation node 6 of the photodiode 1.
At readout, they are completely transferred to the FD node 7 as the input of the amp transistor 4 of the source-follower circuit via the transfer transistor 2.
At transfer, the FD node 7 is floated, and has a parasitic capacity 14 for the ground substrate and other wires at fixed potentials.
Given that the amount of accumulated charge is Q and the parasitic capacity value is Cf, the amount of potential change ΔVf is as below.ΔVf=Q/C 
An NMOS transistor is typically used for the source-follower circuit as the amp transistor 4, and generates inherent random noise Nr.
Therefore, given that its gain is G, the S/N-ratio of the accumulated signal generated in an output node 15 of the source-follower circuit is {G·ΔVf/Nr}.
Since G and Nr are nearly constant if the parameter of the amp transistor 4 is determined, the magnitude of ΔVf directly affects the imaging performance.
FIGS. 4A to 4D show a potential transition with the readout and transfer operation using the pixel circuit as shown in FIG. 1 and FIG. 3.
The potential of each node is shown with the positive potential direction downward and the negative potential direction upward in the drawing. Each node serves as a well for accumulating electrons having negative charge, and, as the well is filled with electrons, the potential rises upward, i.e., in the negative potential direction.
[Step ST1]
At step ST1 in FIG. 4A, the accumulation node 6 as the diffusion node of the photodiode 1 is designed so that the bottom of the potential may be about 1.5 V at its complete depletion by positive charge of a fixed number of donors. Here is filled with photoelectrically converted electrons to a saturated condition (about 0 V).
On the other hand, in the channel region of the transfer transistor 2, its potential is modulated in a range of R1 according to the potential provided to the gate electrode, for example, 1 V to 3 V.
Further, the FD node 7 is reset and floated at 2.7 V. This state is made after the node is reset at 3 V, and then, coupled by 0.3 V when the reset transistor is turned back into the low level.
[Step ST2]
At step ST2 in FIG. 4B, when the transfer transistor 2 is turned on, the every one of electrons accumulated in the accumulation node 6 as the diffusion node of the photodiode 1 moves to the channel region of the transfer transistor 2 and the FD node 7 in a distributed manner.
[Step ST3]
At step ST3 in FIG. 4C, when the transfer transistor 2 is turned off, and therefore, the potential of the channel region rises with the rise of the gate electrode, and the electrons accumulated there move to the FD node 7.
[Step ST4]
At step ST4 in FIG. 4D, when the transfer transistor 2 is off, all of the electrons accumulated in the photodiode 1 at step ST1 move to the FD node 7.
Thereby, the source-follower drives the vertical signal line 11 and performs readout of the accumulated signal.
As described above, to realize complete migration of electrons, it is necessary to secure the potential difference M1 between the completely depleted accumulation node 6 of the photodiode 1 and the FD node 7.
Contrary, if the potential difference M1 is not sufficiently secured, the electrons accumulated in the FD node 7 reversely flow to the photodiode 1, and the amount of accumulated charge of the photodiode 1 is not linearly reflected on the readout signal.